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this is information on a product in full production. march 2012 doc id 13095 rev 3 1/57 57 sta529 ffx? audio codec with analog and digital inputs and 2 x 1.2 w (or 2 x 100 mw hp) class-d amplifier datasheet ? production data features up to 96 db dynamic range sample rates from 8 khz to 192 khz ffx ? class-d driver 1.55 v to 1.95 v digital power supply 1.80 v to 3.60 v analog and i/o power supply 18-bit audio processing and class-d ffx ? modulator >90-db snr analog-to-digital converter digital volume control: ? +36 db to -105 db in 0.5-db steps ? software volume update 16-bit adc individual channel and master gain/attenuation automatic invalid input detect mute 2-channel i 2 s input/output data interface digitally controlled pop-free operation 90% efficiency output power for stereo headphones or stereo speakers applications (at thd = 10% and v cc = 3.3 v): ? 45 mw with 32- headphones ? 85 mw with 16- headphones ? 720 mw with 8- speakers ? 1.1 w with 4- speakers applications portable devices ? laptops ? digital cameras ? microless applications tfbga48 vfqfpn52 table 1. device summary order code operating temp. range package packaging sta529q -40 to 85 c vfqfpn52 tray sta529 -40 to 85 c tfbga48 tray www.st.com
contents sta529 2/57 doc id 13095 rev 3 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 connection diagrams and pin descriptions . . . . . . . . . . . . . . . . . . . . . . 8 2.1 tfbga48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 vfqfpn52 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 electrical and thermal specifica tions . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 selclk33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 signal processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 i 2 c interface disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 set fractional pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 adc performance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.1 digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.2 high-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.3 programmable gain amplifier (pga) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 applications scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
sta529 contents doc id 13095 rev 3 3/57 7.4 configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 i 2 s bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3.1 dsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.2 i 2 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.3 pcm/if (non-delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3.4 pcm/if (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.1 data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.6 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.6.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.6.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7.1 current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7.2 current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7.3 random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7.4 random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.1 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.2 general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.1 package tfbga48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.2 package vfqfpn52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
contents sta529 4/57 doc id 13095 rev 3 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
sta529 list of figures doc id 13095 rev 3 5/57 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. connection diagram for tfbga48 (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. connection diagram for vfqfpn52 (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. circuit for crystal drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. pll filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. diagram of input coupling and supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10. right justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11. left justified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12. dsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13. i 2 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. pcm/if (non delayed mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15. pcm/if (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16. i 2 c write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17. i 2 c read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18. package outline (tfbga48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19. package outline (vfqfpn52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
list of tables sta529 6/57 doc id 13095 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description for tfbga48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. pin description for vfqfpn52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. load power at 1% distortion in headphone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. load power at 10% distortion in headphone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. load power at 1% distortion in speaker mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. load power at 10% distortion in speaker mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. pll lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13. master volume offset as a function of register mvol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 14. channel volume as a function of registers lvol and rvol . . . . . . . . . . . . . . . . . . . . . . . 19 table 15. oversampling table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. programmable gain performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 table 17. digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. high-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 19. pin functions in driver-configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 20. master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 22. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 23. package dimensions (tfbga48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 24. package dimensions (vfqfpn52). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
sta529 description doc id 13095 rev 3 7/57 1 description the sta529 is a digital stereo class-d audio amplifier. it includes an audio dsp, an st proprietary high-efficiency class-d driver and cmos power output stage. it is intended for high-efficiency digital-to-power-audio conversion for portable applications. the sta529 also provides output capabilities for ffx ? . in conjunction with a power device, the sta529 provides high-quality digital amplification. the sta529 contains an on-chip volume/gain control. the pwm amplifier achieves greater than 90% efficiency for longer battery life for portable systems. the innovative class-d modulation, allows the sta529 to work without external lc filters and without a heatsink. the sta529 i2cdis pin disables the audio dsp functions and the i 2 c interface provides a direct conversion of the input signal into output power. this conversion is done without the microcontroller. the sta529 is designed for low-power operation with extremely low-current consumption in standby mode. it is available in packages tfbga48 and vfqfpn52. these are very thin packages (1.2 mm thick) ideal for small portable applications. figure 1. block diagram power driver power driver control interface divider pll osc ffx modulator pwm out i/f adc adc serial digital audio interface pga digital volume rst_n tm stby mute powerfault / eadp biclko / pwm1a lrclki lrclko / pwm1b sdatai sdatao / pwm2a gndio vddio gnd33 vcc33 gnd2 gnd1 vcc2 vcc1 vdd gnd biclki avcc agnd xto selclk33 filt vddpll gndpll clkout / pwm2b sda scl i2cdis xti mclk33 out1a out1b out2a out2b vbias inl vhi vcm vlo inr mux mux mux
connection diagrams an d pin descriptions sta529 8/57 doc id 13095 rev 3 2 connection diagrams and pin descriptions this section includes connection diagrams an d pin descriptions for the following packages: tfbga48 vfqfpn52 2.1 tfbga48 package figure 2. connection diagram for tfbga48 (bottom view) table 2. pin description for tfbga48 pin name type description a1 vcc2 supply channel 2 power supply a2 gnd2 ground channel 2 power ground a3 out2a analog output channel 2 half-bridge a output a4 out2b analog output channel 2 half-bridge b output a5 out1b analog output channel 1 half-bridge b output a6 out1a analog output channel 1 half-bridge a output a7 gnd1 ground channel 1 power ground a8 vcc1 supply channel 1 power supply b1 gndio ground i/o ring ground b2 gnd33 ground pre-driver ground b3 out2a analog output channel 2 half-bridge a output b4 out2b analog output channel 2 half-bridge b output f e d c b a 12345678 h g
sta529 connection diagrams and pin descriptions doc id 13095 rev 3 9/57 b5 out1b analog output channel 1 half-bridge b output b6 out1a analog output channel 1 half-bridge a output b7 mute digital input mute (active high) b8 gnd ground digital ground c1 vddio supply i/o ring supply c2 vcc33 supply pre-driver supply c7 clkout / pwm2b digital output buffered clock output / pwm2b ffx c8 vdd supply digital supply d1 xti digital input 1.8v crystal input or master clock input d2 xto digital output 1.8v crystal output d7 rst_n digital input reset (active low) d8 vcm analog i/o adc common mode voltage e1 mclk33 digital input master clock input 3.3-v capable e2 sdatai digital input input serial audio interface data e7 vlo analog input adc low reference voltage e8 agnd ground adc analog ground f1 scl digital input i 2 c serial clock f2 powerfault / eapd digital output power fault signal (active high) / external audio power-down signal f7 vhi analog input adc high reference voltage f8 avdd supply adc analog supply g1 sda digital i/o i 2 c serial data g2 i2cdis digital input i 2 c disable pin (active high) g3 selclk33 digital input master clock input selector: 0: xti selected 1: mclk33 selected g4 sdatao / pwm2a digital output output serial audio interface data / pwm2a ffx g5 lrclko / pwm1b digital i/o output serial audio interface l/r-clock (volume increases when i2cdis = 1) / pwm1b ffx g6 biclko / pwm1a digital i/o output serial audio interface bit-clock (volume decreases when i2cdis = 1) / pwm1a ffx g7 vbias analog i/o adc microphone bias voltage g8 stby digital input standby (active high) h1 filt analog i/o pll loop filter terminal table 2. pin description for tfbga48 (continued) pin name type description
connection diagrams an d pin descriptions sta529 10/57 doc id 13095 rev 3 2.2 vfqfpn52 package figure 3. connection diagram for vfqfpn52 (bottom view) h2 tm digital input test mode (active high) h3 gndpll ground pll analog ground h4 vddpll supply pll analog supply h5 lrclki digital i/o input serial audio interface l/r-clock h6 biclki digital i/o input serial audio interface bit-clock h7 inl analog input adc left channel line input or microphone input h8 inr analog i/o adc right channel line input table 2. pin description for tfbga48 (continued) pin name type description table 3. pin description for vfqfpn52 pin name type description 1 stby digital input standby (active high) 2 inl analog input adc left channel line input or microphone input 3 inr analog i/o adc right channel line input 4 vbias analog i/o adc microphone bias voltage 5 avdd supply adc analog supply 6 vhi analog input adc high reference voltage 7 vlo analog input adc low reference voltage 40 52 26 14 39 27 1 13
sta529 connection diagrams and pin descriptions doc id 13095 rev 3 11/57 8 agnd ground adc analog ground 9 vcm analog i/o adc common mode voltage 10 rst_n digital input reset (active low) 11 clkout / pwm2b digital output buffered clock output / pwm2b ffx 12 gnd1 ground digital ground 13 vdd1 supply digital supply 14 mute digital input mute (active high) 15 vcc1a supply channel 1 half-bridge a power supply 16 out1a analog output channel 1 half-bridge a output 17 gnd1a ground channel 1 half-bridge a power ground 18 gnd1b ground channel 1 half-bridge b power ground 19 out1b analog output channel 1 half-bridge b output 20 vcc1b supply channel 1 half-bridge b power supply 21 vcc2b supply channel 2 half-bridge b power supply 22 out2b analog output channel 2 half-bridge b output 23 gnd2b ground channel 2 half-bridge b power ground 24 gnd2a ground channel 2 half-bridge a power ground 25 out2a analog output channel 2 half-bridge a output 26 vcc2a supply channel 2 half-bridge a power supply 27 gnd33 ground pre-driver ground 28 gndio1 ground i/o ring ground 29 vddio1 supply i/o ring supply 30 vcc33 supply pre-driver supply 31 powerfault / eapd digital output power fault signal (active high) / external audio power down signal 32 tm digital input test mode (active high) 33 i2cdis digital input i 2 c disable pin (active high) 34 scl digital input i 2 c serial clock 35 sda digital i/o i 2 c serial data 36 selclk33 digital input master clock input selector: 0: xti selected 1: mclk33 selected 37 mclk33 digital input master clock input 3.3-v capable 38 xti digital input 1.8v crystal input or master clock input table 3. pin description for vfqfpn52 (continued) pin name type description
connection diagrams an d pin descriptions sta529 12/57 doc id 13095 rev 3 39 xto digital output 1.8v crystal output 40 filt analog i/o pll loop filter terminal 41 gndpll ground pll analog ground 42 vddpll supply pll analog supply 43 gnd2 ground digital ground 44 vdd2 supply digital supply 45 sdatai digital input input serial audio interface data 46 sdatao / pwm2a digital output output serial audio interface data / pwm2a ffx 47 lrclki digital i/o input serial audio interface l/r-clock 48 lrclko / pwm1b digital i/o output serial audio interface l/r-clock (volume increases when i2cdis = 1) / pwm1b ffx 49 gndio2 ground i/o ring ground 50 vddio2 supply i/o ring supply 51 biclki digital i/o input serial audio interface bit-clock 52 biclko / pwm1a digital i/o output serial audio interface bit-clock (volume decreases when i2cdis = 1) / pwm1a ffx table 3. pin description for vfqfpn52 (continued) pin name type description
sta529 electrical and thermal specifications doc id 13095 rev 3 13/57 3 electrical and thermal specifications 3.1 thermal data 3.2 absolute maximum ratings note: all grounds must be within 0.3 v of each other. table 4. thermal data device parameter min typ max unit tfbga48 thermal resistance junction to ambient - 40 - c/w vfqfpn52 thermal resistance junction to ambient - 22 - c/w table 5. absolute maximum ratings pin/symbol description min max unit vdd vdd1 vdd2 digital supply voltage -0.5 +2.5 v avdd adc supply voltage -0.5 +4 v vddpll pll analog supply voltage -0.5 +2.5 v vcc1a vcc1b vcc2a vcc2b power stage supply voltage -0.5 +4 v vcc33 pre-driver supply -0.5 +4 v vddio digital i/o supply -0.5 +4 v t stg storage temperature -40 150 o c t j junction temperature -40 150 o c
electrical and thermal specifications sta529 14/57 doc id 13095 rev 3 3.3 recommended operating conditions table 6. recommended operating conditions symbol parameter min typ max unit vdd vdd1 vdd2 digital supply voltage 1.55 1.80 1.95 v avdd adc supply voltage 1.8 3.3 3.6 v vddpll pll analog supply voltage 1.55 1.80 1.95 v vcc1a vcc1b vcc2a vcc2b power stage supply voltage 1.8 3.0 3.3 v vcc33 pre-driver supply (must be at same level as vcc1a/1b/2a/2b) 1.8 3.0 3.3 v vddio power supply for i/os 1.8 3.0 3.6 v gnd1, gnd2, gnd33 channel 1 and 2 power ground, pre-driver ground - 0 - v gndio ground for i/os - 0 - v v ih 3.3-v supply 2.0 - - v v il 3.3-v supply - - 0.8 v v hyst schmitt trigger hysteresis (vddio) 0.4 - - v t amb ambient operating temperature -40 - 85 o c
sta529 electrical and thermal specifications doc id 13095 rev 3 15/57 3.4 electrical characteristics the electrical specifications in ta bl e 7 below are given for operation under the recommended conditions listed in ta b l e 6 . unless otherwise specified, lrclki frequency (fs) = 48 khz, input frequency = 1 khz, and r load = 32 . table 7. electrical characteristics symbol parameter test conditions min typ max unit eff output power efficiency - - 90 - % r dson output stage n/pmos on- resistance - - 250 380 m istbyl logic power supply current at standby --1.3- a istbyp bridges power supply current in standby --0.7- a iddl logic power supply current at operating --15-ma iddp bridges power supply current at operating --0.5-ma tds low current dead time (static) - - 1 - ns tdd high current dead time (dynamic) --2.5-ns tr rise time - - 3 - ns tf fall time - - 3 - ns dnr dynamic range a-weighted speaker mode - 96 - db snr signal-to-noise ratio (a- weighted) speaker mode - 92 - db thdn total harmonic distortion 0 dbfs input, 8 speakers -0.1-% -6 dbfs input, 8 speakers -0.05-% 0 dbfs input, 32 headphones -0.1-% -6 dbfs input, 32 headphones -0.05-%
electrical and thermal specifications sta529 16/57 doc id 13095 rev 3 the following tables give the output power for 1% and 10% thd levels for headphones and speakers. 3.5 lock time ta bl e 1 2 gives the typical lock time of the pll using the suggested loop filter with 1.8 v supply and 30 o c junction temperature. table 8. load power at 1% distortion in headphone mode load ( ) p (mw) at 1.8 v p (mw) at 3.3 v 16 20 65 32 10 32 table 9. load power at 10% distortion in headphone mode load ( ) p (mw) at 1.8 v p (mw) at 3.3 v 16 25 85 32 13 42 table 10. load power at 1% distortion in speaker mode load ( ) p (mw) at 1.8 v p (mw) at 3.3 v 4 310 860 8 166 560 16 86 290 32 43 147 table 11. load power at 10% distortion in speaker mode load ( ) p (mw) at 1.8 v p (mw) at 3.3 v 4 400 1100 8 216 720 16 112 380 32 57 200 table 12. pll lock time parameter value lock time 200 s
sta529 input clock doc id 13095 rev 3 17/57 4 input clock 4.1 selclk33 in sta529 the oversampling clock comes from mclk33 or from pin xti. the selection is done by applying the appropriate voltage to pin selclk33. if selclk33 is logical 1 then mclk33 is selected, otherwise xti is selected. if an external crystal is used, selclk33 pin must be connected to gnd and the suggested circuit shown below should be used. figure 4. circuit for crystal drive sta529 external components
digital processing sta529 18/57 doc id 13095 rev 3 5 digital processing the sta529 processor block is a digital block providing two channels of audio processing and channel-mapp ing capability. 5.1 signal processing flow i 2 s or stereo adc data can be selected. the i 2 s frequency range is 8 khz to 192 khz. the adc sampling frequency can be selected between 8 khz and 48 khz. 5.2 i 2 c interface disable when pin i2cdis = 1, the sda, scl, lrclko and biclko pins can be pulled high or low to change certain parameters of operation. sda = 0: ffx input comes from adc sda = 1: ffx input comes from digital audio interface scl = 0: binary output mode (binary soft start/stop enabled) scl = 1: phase shift output mode lrclko = 0: no volume change lrclko = 1: channel volume up on both channel biclko = 0: no volume change biclko = 1: channel volume down on both xchannel. at power up, the channel volume is set to -60 db. when holding pin lrclko = 1 and pin biclko = 1 simultaneously, the channel volume is set to 0 db. a high pulse on pin lrclko causes a channel volume change of +0.5 db and a high pulse on pin biclko causes a channel volume change of -0.5 db.
sta529 digital processing doc id 13095 rev 3 19/57 5.3 volume control and gain the volume control structure of the sta529 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel?s volume setting. the individual channel volumes are adjustable in 0.5-db steps from +36 db to -91.5 db. as an example, if register lvol = 0x00 or +36 db and register mvol = 0x18 or -12 db, then the total gain for the left channel is +24 db. when the mute bit is set to 1, all channels are muted. the volume control provides a soft mute with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (around 48 khz). table 13. master volume offset as a function of register mvol mvol[7:0] volume offset from channel value 0x00 0 db 0x01 -0.5 db 0x02 -1db ?? 0x78 -60 db ?? 0xfe -105 db 0xff hard master mute table 14. channel volume as a function of registers lvol and rvol lvol/rvol[7:0] volume 0x00 +36 db 0x01 +35.5 db 0x02 +35 db ?? 0x47 +0.5 db 0x48 0db 0x49 -0.5 db ?? ?? 0xff -91.5 db
pll sta529 20/57 doc id 13095 rev 3 6 pll figure 5 shows the main components of the pll. figure 5. pll block diagram 6.1 functional description phase/frequency detector the phase/frequency detector (pfd) comp ares the phase difference between the corresponding rising edges of infin and fbclk, (clock output from the loop frequency divider) by generating voltage pulses with widths proportional to the input phase error. charge pump and loop filter this block converts the voltage pulses from the phase/frequency detector to current pulses which charge the loop filter and generate the control voltage for the voltage-controlled oscillator. the loop filter is placed external to the pll on pin filt. voltage controlled oscillator the voltage controlled oscillator (vco) is t he oscillator inside th e pll. it produces a frequency (f vco ) proportional to the input control voltage. input frequency output frequency divider loop frequency divider clkin lockp f vco idf lock detect infin fbclk phase buffer fractional controller vco infin fbclk dither_disable frac_input ndiv phi infout divider charge refout lf filt vcont pump and loop filter strb strb_bypass frac_ctrl frequency divider (pfd)
sta529 pll doc id 13095 rev 3 21/57 input frequency divider this frequency divider divides the pll input clock clkin by a factor called the input division factor (idf) to generate the pfd input frequency infin. loop frequency divider this frequency divider is present within the pll for dividing f vco by a factor called the loop division factor (ldf). the output of this block is clock fbclk. output frequency divider the output frequency divider divides f vco by the output division factor (odf) to produce the output clock phi and the clock to the core. in the sta529, odf = 2 and cannot be reconfigured. lock-detect circuit the output of this block (signal lockp) is asserted high when the pll enters the state of coarse lock in which the output frequency is within 10%, approximately, of the desired frequency. lockp is refreshed every 32 cycles of clock infin. the generated value is based on the result of comparing the number of fbclk cycles in a window of 14 infin cycles. the different cases generated after comparison are as follows. if lockp is already at 0, then in the next refresh cycle lockp goes to 1 if the number of fbclk cycles in the 14-cycle infin wi ndow is 13, 14, or 15. otherwise lockp stays at 0. if lockp is already at 1, then in the next refresh cycle lockp goes to 0 if the number of fbclk cycles in the 25-cycle infin wi ndow is less than 11 or higher than 17, otherwise lockp stays at 1. if lockp is already at 1 and clkin is lost (no longer present on the input pin), lockp stays at 1. in this case, the pll is unlocked. pll filter figure 6 below shows the pll filter circuit. recommended values are r1 = 12.5 k , c1 = 250 pf and c2 = 82 pf. figure 6. pll filter circuit table 12 on page 16 gives a typical lock time value for the pll. c2 r1 c1 vc ground
pll sta529 22/57 doc id 13095 rev 3 6.2 configuration examples the sta529 pll can be configured in two ways: default startup configuration direct pll programming the default startup configuration reads the device defaults. with this configuration, it is not necessary to program the pll dividers directly as preset values are used. in this mode, the oversampling ratio between pins xti (or mclk33) and lrclki is fixed to 256. the direct pll programming bypasses the automatic presets allowing direct programming of the pll dividers. the output pll frequency can be determined by the following equations. output division factor: odf = 2. relation between input and output clock frequency: f infin = f xti / idf. if register bit pllcfg0.frac_ctrl = 1 f vco = f infin * (ldf + fract / 2 16 + 1 / 2 17 ) f phi = f vco / odf. when register bit pllcfg0.dither_disable[1] = 1, the 1/2 17 factor is not in the multiplication. this is recommended in order to keep register bit pllcfg0.dither_disable[1] = 0, otherwise there can be spuri ous signals in the output clock spectrum. if register bit pllcfg0.frac_ctrl = 0, then: f vco = f infin * ldf f phi = f vco / odf. in the above equations: fract = decimal equivalent of register bit pllcfg1.frac_input[15:0] idf = input division factor ldf = loop division factor odf = output division factor = 2 f infin = infin frequency f xti = xti frequency f vco = vco frequency f phi = frequency of the pll output clock. when selecting the values for idf, ldf and fract, ensure that the following limits are maintained: 2.048 mhz < f xti < 49.152 mhz 2.048 mhz < f infin < 16.384 mhz 65.536 mhz < f vco < 98.304 mhz there are also some additional constraints on idf and ldf. idf should be greater than 0, ldf should be greater than 5 if frac_ctrl = 0 and greater than 8 if frac_ctrl = 1.
sta529 pll doc id 13095 rev 3 23/57 when automatic settings are not used, the pll must be configured to generate an internal frequency, f phi , of n * fs, where fs is the frequency of pin lrclki. values for n are given in ta bl e 1 5 . example 1 f xti = 13 mhz and fs = 44.1 khz idf should be equal to 3 otherwise ldf becomes less than 8 (frac_ctrl must be 1): ldf = floor(45.1584 / (13 / idf)) = 10 fract = round([(45.1584 / (13 / idf)) - floor(45.1584 / (13 / idf))] * 2 16 ) = 27602. where: floor means rounded down and round means rounded to nearest integer. using the above configuration, the system clock is 45.15841675 mhz, the approximate static error is 16 hz (that is, 0.5 ppm). example 2 f xti = 19.2 mhz and fs = 48 khz idf should be equal to 4 otherwise ldf become less than 8 (frac_ctrl must be 1): ldf = floor(49.152 / (19.2 / idf)) = 10 fract = round([(49.152 / (19.2 / idf)) - floor(49.152 / (19.2 / idf))] * 2 16 ) = 15728. using the above configuration, the system cl ock is 49.151953125 mhz, the approximate static error is 47 hz (that is, 1 ppm). table 15. oversampling table fs (khz) n f phi (mhz) 8 4096 32.768 11.025 4096 45.1584 12 4096 49.152 16 2048 32.768 22.05 2048 45.1584 24 2048 49.152 32 1024 32.768 44.1 1024 45.1584 48 1024 49.152 64 512 32.768 88.2 512 45.1584 96 512 49.152 128 256 32.768 176.4 256 45.1584 192 256 49.152
pll sta529 24/57 doc id 13095 rev 3 6.3 set fractional pll the following procedure is mandatory to configure the fractional pll: 1. set bit d7 reg 0x18 ( pll_byp_unl) to "1" 2. write reg 0x17 (pllcfg3) 3. write reg 0x14 (pllcfg0) 4. write reg 0x15 (pllcfg1) 5. write reg 0x16 (pllcfg2) 6. set bit d7 reg 0x18 ( pll_byp_unl) to "0"
sta529 adc doc id 13095 rev 3 25/57 7 adc 7.1 adc performance values 7.2 functional description the sta529 analog input is provided through a low-power, low-voltage, 16-bit stereo audio analog-to-digital converter front end designed for audio applications. it includes a programmable gain amplifier, anti-aliasing filter, low-noise microphone biasing circuit, third-order mash2-1 delta-sigma modulator, digital decimating filter and a first-order dc-removal filter. the adc works in the microphone input (mic-in) mode and in the line-input mode. if the line input mode is selected, the adc is configured in stereo and all conversion channels are active. if the microphone input mode is selected, the adc is configured in mono. the mono channel is routed through the left conversion path, and the right conversion path is kept in power-down mode to minimize power consumption. a programmable gain amplifier (pga) is available in mic-in mode, making it possible to amplify the signal from 0 to +42 db in steps of 6db. table 16. programmable gain performance parameter min typ max unit dynamic range 1 khz, a-weighted (3.3 v supply) 92 db dynamic range 1 khz, a-weighted (1.8 v supply) 84 db sndr 1 khz, a-weighted (3.3 v supply) 92 db sndr 1 khz, a-weighted (1.8 v supply) 84 db thd 1 khz (-1 db input) (3.3 v supply) -85 db thd 1 khz (-1 db input) (1.8 v supply) -75 db cross talk (3.3 v supply) -80 db cross talk (1.8 v supply) -60 db
adc sta529 26/57 doc id 13095 rev 3 7.2.1 digital filter characteristics 7.2.2 high-pass filter characteristics 7.2.3 programmable gain amplifier (pga) the pga is available in mic-in mode only. the input signal can be amplified from 0 to 42 db in 6-db steps via bits pga of register adccfg on page 49 . table 17. digital filter characteristics parameter typical unit pass band 0.4535 * fs khz pass-band ripple: fs mode fs_by_2 mode fs_by_4 mode 0.08 at 44.1 khz 0.08 at 22.05 khz 0.08 at 11.025 khz db db db stop-band attenuation: fs mode fs_by_2 mode fs_by_4 mode 45 at 44.1 khz 45 at 22.05 khz 45 at 11.025 khz db db db group delay: fs mode fs_by_2 mode fs_by_4 mode 0.4 at 32 khz 0.7 at 16 khz 1.4 at 8 khz ms ms ms table 18. high-pass filter characteristics parameter typical unit frequency response: -3 db -0.08 db 7 50 hz hz phase deviation at 20 hz 19.35 degree passband ripple 0.08 db
sta529 adc doc id 13095 rev 3 27/57 7.3 applications scheme figure 7. diagram of input coupling and supply decoupling 7.4 configuration examples the adc sampling frequency can be selected from three values: normal (from 32 khz to 48 khz) low (from 16 khz to 24 khz) very-low (from 8 khz to 12 khz) the setting is done through bits adc_fs_range of register misc on page 50 . for all other settings register adccfg on page 49 is used. ac coupled dc coupled dc coupled ac coupled c9 c0 c1 c5 c2 c6 c3 c7 c4 c8 3v, 3a supply vssa vssa r1 inl inr avdd agnd vhi vlo vcm vbias c1, c2, c3, c4 = 10 nf (these capacitors must be placed very close to their respective ic pins) c5, c6, c7 = 33 f (low esr and esl capacitors are recommended) vssa plane must be different from other ground plane 3v, 3a must be a low-noise supply and separate from other supplies r1 = 500 c8 = 10 f c9, c0 = 1 f
driver configuration sta529 28/57 doc id 13095 rev 3 8 driver configuration a driver configuration is available that allows pwm commands to be used on an external power device. for this purpose, the output serial audio interface is disabled and the respective pins have an alternative name and a new function, as shown in ta b l e 1 9 . the driver configuration is selected with the two programmable registers, pwmint1 = 0x93 and pwmint2 = 0x81, on page 51 . 8.1 i 2 s bypass a configuration is available which allows the passing of the i 2 s input signal straight to the i 2 s output signal. this configuration is set using two programmable registers pwmint1 = 0x93 and pwmint2 = 0x80. table 19. pin functions in driver-configuration mode pin alternative pin name and function biclko pwm1a (external bridge pwm command for output 1a) lrclko pwm1b (external bridge pwm command for output 1b) sdatao pwm2a (external bridge pwm command for output 2a) clkout pwm2b (external bridge pwm command for output 2b) powerfault eadp (external audio power-down signal)
sta529 serial audio interface doc id 13095 rev 3 29/57 9 serial audio interface the serial-to-parallel interface and the parallel-to-serial interface can have different sampling rates. the following terms are used in this section: biclk active edge: pins sdatai, sdatao, lrcl ki, lrclko always change synchronously with bitclk active edges. the active edge can be configured as a rising or falling edge via register programming. biclk strobe edge: pins sdatai, sdatao, lrclki, lrclko should be stable near biclk strobe edges, the slave device is able to use strobe edges to latch serial data internally. 9.1 master mode in this mode, pins biclki/biclko and pins lrclki/lrclko are configured as outputs. figure 8. master mode table 20. master mode symbol parameter min typ max unit t dl lrclki/lrclko propagation delay from biclk active edge 010ns t dda sdatao propagation delay from biclki/o active edge 0 15 ns t dst sdatai setup time to biclki/o strobing edge 10 ns t dht sdatai hold time from biclki/o strobing edge 10 ns biclki/ biclko lrclki/ lrclko sdatao sdatai t dst t dht t dl t dda
serial audio interface sta529 30/57 doc id 13095 rev 3 9.2 slave mode in this mode, pins biclki/o and pins lrclki/o are configured as inputs. figure 9. slave mode table 21. slave mode symbol parameter min typ max unit t bcy biclk cycle time 50 ns t bch biclk pulse width high 20 ns t bcl biclk pulse width low 20 ns t lrsu lrclki/lrclko setup time to biclk strobing edge 10 ns t lrh lrclki/lrclko hold time to biclk strobing edge 10 ns t ds sdatao setup time to biclk strobing edge 25 ns t dh sdatao hold time to biclk strobing edge 25 ns t dd sdatai propagation delay from biclk active edge 0 10 ns biclki/ biclko lrclki/ lrclko sdatai sdatao t bch t bcl t bcy t ds t lrh t lrsu t dh t dd
sta529 serial audio interface doc id 13095 rev 3 31/57 9.3 serial formats different audio formats are supported in both master and slave modes. clock and data configurations can be customized to match most of the serial audio protocols available on the market. data length can be customized to 8, 16, 24 or 32 bits. figure 10. right justified figure 11. left justified 123 n -1 n lrclki/ lrclko biclki/ biclko sdatai/ sdatao 123 n -1 n 123 n -1 n lrclki/ lrclko biclki/ biclko sdatai/ sdatao 123 n -1 n
serial audio interface sta529 32/57 doc id 13095 rev 3 9.3.1 dsp figure 12. dsp 9.3.2 i 2 s figure 13. i 2 s 123 n -1 n lrclki/ lrclko biclki/ biclko sdatai/ sdatao 123 n -1 n left right 123 n -1 n lrclki/ lrclko biclki/ biclko sdatai/ sdatao 123 n -1 n
sta529 serial audio interface doc id 13095 rev 3 33/57 9.3.3 pcm/if (non-delayed mode) msb first 16-bit data figure 14. pcm/if (non-delayed mode) 9.3.4 pcm/if (delayed mode) msb first 16-bit data figure 15. pcm/if (delayed mode) lrclki/ lrclko biclki/ biclko sdatai/ sdatao 123 n -1 n any width lrclki/ lrclko biclki/ biclko sdatai/ sdatao 123 n -1 n
i 2 c interface sta529 34/57 doc id 13095 rev 3 10 i 2 c interface 10.1 data transition and change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 10.2 start condition a start condition is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 10.3 stop condition a stop condition is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between the sta529 and the master bus. 10.4 data input during data input, the sta529 samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 10.5 device addressing to start communication between the master and the sta529, the master must initiate with a start condition. following this, the master sends 8 bits (msb first) on the sda line corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the sta529, the i 2 c interface has the device address 0x34. the 8th bit (lsb) identifies the read or write operation (r/w). it is set to 1 in read mode and 0 in write mode. after the start condition, the sta529 waits for its device address on sda. when a match is found, it acknowledges the identification on sda during the 9th bit time. the byte following the device identification byte is the internal space address.
sta529 i 2 c interface doc id 13095 rev 3 35/57 10.6 write operation following the start condition the master sends a device select code with the r/w bit set to 0. the sta529 acknowledges this and then writes to the byte of the internal address. after receiving the internal byte address, the sta529 responds with an acknowledgement. 10.6.1 byte write in the byte-write mode the master sends one data byte. this is acknowledged by the sta529. the master then terminates the transfer by generating a stop condition. 10.6.2 multi-byte write the multi-byte write modes can start from any internal address. the master generates a stop condition which terminates the transfer. 10.7 read operation 10.7.1 current address byte read following the start condition the master sends a device select code with bit r/w set to 1. the sta529 acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 10.7.2 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the sta529. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. 10.7.3 random address byte read following the start condition the master sends a device select code with bit r/w set to 0. the sta529 acknowledges this and then the master writes the internal address byte. after receiving the internal byte address, the sta529 again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with bit r/w set to 1. the sta529 acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition.
i 2 c interface sta529 36/57 doc id 13095 rev 3 10.7.4 random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes are read from sequential addresses within the sta529. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. figure 16. i 2 c write operations figure 17. i 2 c read operations r/w multibyte stop start sub address data in data in ack ack ack ack dev address write r/w byte stop start sub address data in ack ack ack dev address write r/w random stop start sub address start data ack ack ack no ack dev address address r/w current stop start data ack no ack dev address address read dev address r/w read sequential stop start data data ack ack ack no ack dev address current data read r/w=high r/w sequential start sub address start data ack ack ack ack dev address random dev address r/w read stop data ack no ack data
sta529 registers doc id 13095 rev 3 37/57 11 registers this section describes the set-up register used in the device. 11.1 summary table 22. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 ffxcfg0 mute pow_stby soft_ vol_on bin_soft start tim_soft_vol[3:0] 0x01 ffxcfg1 l1_r2 mute_on_ invalid pwm_mode[1:0] pwm_shift[1:0] reserved 0x02 mvol set_vol_master[7:0] 0x03 lvol set_vol_left[7:0] 0x04 rvol set_vol_right[7:0] 0x05 ttf0 tim_ts_fault[15:8] 0x06 ttf1 tim_ts_fault[7:0] 0x07 ttp0 tim_ts_powup[15:8] 0x08 ttp1 tim_ts_powup[7:0] 0x0a s2pcfg0 biclk_ strb lrclk_ left share_ bilr msb_first data_format[2:0] master_ mode 0x0b s2pcfg1 pdata_length[1:0] biclk_os[1:0] map_l[1:0] map_r[1:0] 0x0c p2scfg0 biclk_ strb lrclk_ left sdatao_ act msb_first data_format[2:0] master_ mode 0x0d p2scfg1 pdata_length[1:0] biclk_os[1:0] map_l[1:0] map_r[1:0] 0x14 pllcfg0 pll_direc t_prog frac_ ctrl dither_disable[1:0] idf[3:0] 0x15 pllcfg1 frac_input[15:8] 0x16 pllcfg2 frac_input[7:0] 0x17 pllcfg3 strb strb_ bypass ndiv[5:0] 0x18 pllpfe pll_ byp_ unl biclk2pll pll_pwdn pfe1a pfe1b pfe2a pfe2b reset_ fault 0x19 pllst pll_ unlock pll_pwd_ state pll_byp_ state reserved 0x1e adccfg pga[2:0] insel stby bypass_ calib clkenbl reserved 0x1f ckocfg clkout_ dis clkout_sel[1:0] reserved 0x20 misc osc_dis p2p_fs_range[2:0] adc_fs_range[1:0] p2p_in_ adc core_ clkenbl 0x21 padst0 reserved 0x22 padst1 reserved
registers sta529 38/57 doc id 13095 rev 3 all other registers not mentioned here are reserved and must not be used. 11.2 general registers ffxcfg0 ffx configuration address: 0x00 type: r/w buffer: no reset: 0x75 description: 0x23 ffxst reserved invalid_ inp_fbk mute_ int_fbk reserved 0x28 bistrun reserved 0x29 bistst0 reserved 0x2a bistst1 reserved 0x2b bistst2 reserved 0x2d pwmint1 pwm_int[15:8] 0x2e pwmint2 pwm_int[7:0] 0x32 powst power down pow_ tristate pow_ fault1a pow_ fault1b pow_ fault2a pow_ fault2b reserved table 22. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mute pow_stby soft_vol_on bin_ softstart tim_soft_vol[3:0] 7mute: 0: standard operation (default) 1: ffx output is zero (muted condition) 6pow_stby: 0: ffx bridge is in power-up mode 1: ffx bridge is in standby mode (default) 5 soft_vol_on: 0: smooth transition not active 1: smooth transition when cha nging volume control (default) 4 bin_softstart: reserved (1: default) 3:0 tim_soft_vol: volume control time step for any 0.5 db volume change time is (2 tim_soft_vol ) * 20.83 s default value: 0101. this value means 666.66 s
sta529 registers doc id 13095 rev 3 39/57 ffxcfg1 configuration address: 0x01 type: r/w buffer: no reset: 0xf8 description: mvol master volume control address: 0x02 type: r/w buffer: no reset: 0x00 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l1_r2 mute_on_ invalid pwm_mode[1:0] pwm_shift[1:0] res res 7 l1_r2: channel mapping: 0: right channel is mapped to output channel 1 and left channel is mapped to output channel 2 1: left channel is mapped to output channel 1 and right channel is mapped to output channel 2 (default) 6 mute_on_ invalid: mutes pwm outputs if invalid digital data is received: 0: outputs are not muted 1: outputs are muted (default) 5:4 pwm_mode[1:0]: 00: binary (output b is opposite of output a) 01: binary headphones (output b is 50% duty cycle) 10: reserved, do not use 11: phase shift (default) 3:2 pwm_shift[1:0]: 10: default pwm period-shift between channels 1 and 2 value is n * 90 o default is 180 o 1:0 reserved (00: default) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set_vol_master[7:0] 7:0 set_vol_master[7:0]: master volume control: from 0 db to -127.5 db in 0.5-db steps default value (0x00) corresponds to 0 db
registers sta529 40/57 doc id 13095 rev 3 lvol left channel volume control address: 0x03 type: r/w buffer: no reset: 0x48 description: rvol right channel volume control address: 0x04 type: r/w buffer: no reset: 0x48 description: ttf0 tristate time after fault (msbs) address: 0x05 type: r/w buffer: no reset: 0x00 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set_vol_left[7:0] 7:0 set_vol_left[7:0]: left channel volume control: left channel volume control (from +36 db to -91.5 db in 0.5-db steps) default value (0x48) corresponds to 0 db bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set_vol_right[7:0] 7:0 set_vol_right[7:0]: righ t channel volume control: right channel volume control (from +36 db to -91.5 db in 0.5-db steps) default value (0x00) corresponds to 0 db bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tim_ts_fault[15:8] 7:0 msbs of tim_ts_fault[15:0]: see register ttf1 .
sta529 registers doc id 13095 rev 3 41/57 ttf1 tri-state time after fault (lsbs) address: 0x06 type: r/w buffer: no reset: 0x02 description: ttp0 tri-state time after power-up (msbs) address: 0x07 type: r/w buffer: no reset: 0x00 description: ttp1 tristate time after power-up (lsbs) address: 0x08 type: r/w buffer: no reset: 0x02 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tim_ts_fault[7:0] 7:0 lsbs of tim_ts_fault [15:0]: time in which power is held in tristate mode after a fault signal: time is tim_ts_fault * 83.33 s. default value (0x0002) corresponds to 166.66 s tristate time after fault bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tim_ts_powup[15:8] 7:0 msbs of tim_ts_powup[15:0]: see register ttp1 below. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tim_ts_powup[7:0] 7:0 lsbs of tim_ts_powup [15:0]: time in which power is held in tri-state mode after a power-up signal: time is tim_ts_powup * 83.33 s default value (0x0002) corresponds to 166.66 s tristate time after power-up
registers sta529 42/57 doc id 13095 rev 3 s2pcfg0 serial to parallel audio interface configuration address: 0x0a type: r/w buffer: no reset: 0xd2 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 biclk_strb lrclk_left share_bilr msb_first data_format[2:0] master_ mode 7 biclk_strb: 0: bit clock strobe edge is falling edge, bit clock active edge is rising edge 1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default) 6 lrclk_left: 0: left/right clock is low for left channel, high for right channel 1: left/right clock is high for left ch annel, low for right channel (default) 5 share_bilr: 0: default 1: left/right clock and bit clock are shared between serial to parallel interface and parallel to serial interface, biclki and lrclki are used 4 msb_first: 0: lsb first 1: msb first (default) 3:1 data_format[2:0]: serial interface protocol format: 000: left justified 001: i 2 s (default) 010: right justified 100: pcm no delay 101: pcm delay 111: dsp 0 master_mode: 0: sai outis in slave mode (default) 1: sai outis in master mode
sta529 registers doc id 13095 rev 3 43/57 s2pcfg1 serial-to-parallel audio interface configuration address: 0x0b type: r/w buffer: no reset: 0x91 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pdata_length[1:0] biclk_os[1:0] map_l[1:0] map_r[1:0] 7:6 pdata_length[1:0]: serial-to-pa rallel interface data length: length is (n+1) * 8 bit default (10) is 24 bit 5:4 biclk_os[1:0]: bit clock oversampling: value is (n+1) * 32 * fs (where fs = sampling frequency) default (01) is 64 fs 3:2 map_l[1:0]: left data-mapping slot: value is nth slot default (00) is slot 0 1:0 map_r[1:0]: right data-mapping slot: value is nth slot default (01) is slot 1
registers sta529 44/57 doc id 13095 rev 3 p2scfg0 parallel-to-serial audi o interface configuration address: 0x0c type: r/w buffer: no reset: 0xd3 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 biclk_ strb lrclk_left sdatao_act msb_first data_format[2:0] master_ mode 7 biclk_strb: defines the bit clock edges: 0: strobe is falling edge, active edge is rising 1: strobe is rising edge, active edge is falling (default) 6 lrclk_left: defines the channel for the lr clock: 0: clock is low for left channel, high for right channel 1: clock is high for left channel, low for right channel (default) 5 sdatao_ act: sets the behavior of pin sdatao: 0: output is tristated when no data is sent (default) 1: output is never in tri-state (it is 0 when no data is sent) 4 msb_first: data alignment in the protocol for sdatai and sdatao: 0: lsb is the first bit 1: msb is the first bit (default) 3:1 data_format[2:0]: serial interface protocol format: 000: left justified 001: i 2 s (default) 010: right justified 100: pcm no delay 101: pcm delay 111: dsp 0 master_ mode: selects serial interface master/slave mode: 0: slave 1: master (default)
sta529 registers doc id 13095 rev 3 45/57 p2scfg1 parallel-to-serial audi o interface configuration address: 0x0d type: r/w buffer: no reset: 0x91 description: pllcfg0 pll configuration address: 0x14 type: r/w buffer: no reset: 0x00 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pdata_length[1:0] biclk_os[1:0] map_l[1:0] map_r[1:0] 7:6 pdata_length[1:0]: serial-to-pa rallel interface data length: length is (pdata_length+1) * 8 bit default (10) is 24 bits 5:4 biclk_os[1:0]: bit clock oversampling: value is (biclk_os+1) * 32 * fs default (01) is 64 fs 3:2 map_l[1:0]: left data-mapping slot: value is nth slot default (00) is slot0 1:0 map_r[1:0]: right ch annel data-mapping slot: value is nth slot default (01) is slot1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll_direct_ prog frac_ctrl dither_disable[1:0] idf[3:0] 7 pll_direct_prog: pll programming: 0: default 1: pll is programmed according to the pllcfg register settings
registers sta529 46/57 doc id 13095 rev 3 pllcfg1 pll confi guration (msbs) address: 0x15 type: r/w buffer: no reset: 0x00 description: pllcfg2 pll configuration (lsbs) address: 0x16 type: r/w buffer: no reset: 0x00 description: 6 frac_ctrl: 0: default 1: pll fractional-frequency synthesis is enabled 5:4 dither_disable[1:0]: 00: default 1x: disables rectangular phase frequency divider dither input to fractional control x1: disables triangular phase frequency divider dither input to fractional control the mentioned blocks are shown in figure 5 . 3:0 idf[3:0]: pll input division factor: 0000: idf = 1 (default) 0001: idf = 1 0010: idf = 2 ? 1111: idf = 15 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frac_input[15:8] 7:0 frac_input[15:8]: msbs of frac_input[15: 0] used to set the fractional part of pll multiplication factor bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frac_input[7:0] 7:0 frac_input[7:0]: lsbs of frac_input[15:0] used to set the fractional part of pll multiplication factor
sta529 registers doc id 13095 rev 3 47/57 pllcfg3 pll configuration address: 0x17 type: r/w buffer: no reset: 0x00 description: pllpfe pll/pop-free configuration address: 0x18 type: r/w buffer: no reset: 0x00 description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 strb strb_bypass ndiv[5:0] 7 strb: asynchronous strobe input to the fractional controller: 0: default 6 strb_bypass: standby bypass: 0: strb signal is not bypassed (default) 1: strb signal is bypassed 5:0 ndiv[5:0]: pll multiplicati on factor (integral part) named as loop division factor: 0000 xx: ldf = na 0001 00: ldf = na 0001 01: ldf = 5 ... 1101 11: ldf = 55 111x xx: ldf = na 0000 00: default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll_byp_unl biclk2pll pll_pwdn pfe1a pfe1b pfe2a pfe2b reset_fault 7 pll_byp_unl: pll bypass: 0: pll is not bypassed (default) 1: pll is bypassed when not locked 6 biclk2pll: 0: default 1: biclki is input to pll 5 pll_pwdn: 0: default 1: pll is in power-down mode
registers sta529 48/57 doc id 13095 rev 3 pllst pll status address: 0x19 type: ro buffer: no reset: undefined description: 4pfe1a: 0: default 1: pop-free resistances are connected to output 1a 3pfe1b: 0: default 1: pop-free resistances are connected to output 1b 2pfe2a: 0: default 1: pop-free resistances are connected to output 2a 1pfe2b: 0: default 1: pop-free resistances are connected to output 2b 0 reset_fault: 0: default 1: fault signal in the i 2 c register powst is reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll_unlock pll_pwd_ state pll_byp_ state reserved 7 pll_unlock: pll unlock state: 0: pll is not in unlock state 1: pll is in unlock state 6 pll_pwd_ state: pll power-down state: 0: pll is not in power-down state 1: pll is in power-down state 5 pll_byp_state: pll bypass state: 0: pll is not in bypass state 1: pll is in bypass state 4:0 reserved
sta529 registers doc id 13095 rev 3 49/57 adccfg adc configuration address: 0x1e type: ro buffer: no reset: undefined description: ckocfg output clock configuration address: 0x1f type: r/w buffer: no reset: undefined description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pga[2:0] insel stby bypass_calib clkenbl reserved 7:5 pga[2:0]: gain selection bits for the adc programmable gain amplifier: 000: default values are from 0 to 42 db in 6 db steps 4 insel: 0: line input selected (default) 1: microphone input selected (it must be applied to inl line) 3 stby: adc standby mode: 0: adc in power-up mode (default) 1: adc in standby mode 2 bypass_calib: 0: adc dc-removal block not bypassed (default) 1: adc dc-removal block bypassed 1 clkenbl: clock enable: 0: system clock not enabled 1: system clock available at adc input (default) 0reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkout_dis clkout_sel[1:]] reserved 7 clkout_dis: clkout pad disabled 0: default 1: enabled 6:5 clkout_sel[1:0]: 00: default the clkout output frequency is the pll output frequency divided by 2 clkout_sel 4:0 reserved
registers sta529 50/57 doc id 13095 rev 3 misc miscellaneous configuration address: 0x20 type: r/w buffer: no reset: 0x20 description: ffxst ffx status address: 0x23 type: ro buffer: no reset: undefined bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osc_dis p2p_fs_range[2:0] a dc_fs_range[1:0] p2p_in_adc core_ clkenbl 7 osc_dis: enable/disable crystal oscillator: 0: default 1: disabled 6:4 p2p_fs_range[2:0]: ffx audio frequency range: 000: very low (fs = 8 to 12 khz) 001: low (fs = 16 to 24 khz) 010: normal (fs = 32 to 48 khz) (default) 011: high (fs = 64 to 96 khz) 1x: very high (fs = 128 to 192 khz) 3:2 adc_fs_range[2:0]: adc audio frequency range: 00: normal (fs = 32 to 48 khz) (default) 01: low (fs = 16 to 24 khz) 1x: very low (fs = 8 to 12 khz) 1 p2p_in_adc: ffx input: 0: ffx input is from serial-to-parallel audio interface (default) 1: ffx input is from adc 0 core_clkenbl: availability of system clock: 0: ffx system clock disabled (default) 1: ffx system clock enabled bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved invalid_inp_ fbk mute_int_fbk reserved
sta529 registers doc id 13095 rev 3 51/57 description: pwmint1 pwm driver configuration (msbs) address: 0x2d type: r/w buffer: no reset: 0x00 description: pwmint2 pwm driver configuration (lsbs) address: 0x2e type: r/w buffer: no reset: 0x00 description: 7:3 reserved 2 invalid_inp_fbk: invalid input status: 1: invalid input sent to ffx 1 mute_int_fbk: ffx mute status 1: ffx is in mute state 0 reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm_int[15:8] 7:0 pwm_int[15:8]: msbs of pwm_int[15:0], see chapter 8: driver configuration on page 28 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm_int[7:0] 7:0 pwm_int[7:0]: lsbs of pwm_int[15:0], see chapter 8: driver configuration on page 28
registers sta529 52/57 doc id 13095 rev 3 powst power bridge status register address: 0x32 type: ro buffer: no reset: undefined description: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pow_ powerdown pow_ tristate pow_fault1a pow_fault1b pow_fault2a pow_fault2b reserved 7 pow_powerdown: power-down bridge: 0: not in power-down state 1: power-down state 6 pow_tristate: 1: power bridge is in tristate 5pow_fault1a: 1: power bridge 1a is in fault state 4pow_fault1b: 1: power bridge 1b is in fault state 3pow_fault2a: 1: power bridge 2a is in fault state 2pow_fault2b: 1: power bridge 2b is in fault state 1:0 reserved
sta529 package mechanical data doc id 13095 rev 3 53/57 12 package mechanical data this section contains packaging information for the following packages: tfbga48 vfqfpn52 in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 12.1 package tfbga48 figure 18. package outline (tfbga48)
package mechanical data sta529 54/57 doc id 13095 rev 3 table 23. package dimensions (tfbga48) reference dimensions in mm min typ max a--1.20 a1 0.15 - - a2 - 0.785 - a3 - 0.20 - a4--0.60 b 0.25 0.30 0.35 d 4.85 5.00 5.15 d1 - 3.50 - e 4.85 5.00 5.15 e1 - 3.50 - e - 0.50 - f - 0.75 - ddd - - 0.08 eee - - 0.15 fff - - 0.05
sta529 package mechanical data doc id 13095 rev 3 55/57 12.2 package vfqfpn52 figure 19. package outline (vfqfpn52 ) table 24. package dimensions (vfqfpn52) reference dimensions in mm min typ max a 0.800 0.900 1.000 a1 - 0.020 0.050 a2 - 0.650 1.000 a3 - 0.250 - b 0.180 0.230 0.300 d 7.875 8.000 8.125 d2 2.750 5.700 6.250 e 7.875 8.000 8.125 e2 2.750 5.700 6.250 e 0.450 0.500 0.550 l 0.350 0.550 0.750 ddd - - 0.080
revision history sta529 56/57 doc id 13095 rev 3 13 revision history table 25. document revision history date revision changes 25-jan-2007 1 initial release. 09-apr-2010 2 complete update and change in presentation 30-mar-2012 3 updated features added section 6.3: set fractional pll updated section 7.2: functional description minor textual updates
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